The electronics industry continues to rely upon advances in semiconductor manufacturing technology to realize higher-functioning devices while improving reliability and cost. For many applications, the manufacture of such devices is complex, and maintaining cost-effective manufacturing processes while concurrently maintaining or improving product quality is difficult to accomplish. As the requirements for device performance and cost become more demanding, realizing a successful manufacturing process becomes more difficult.
The increased complexity of semiconductor devices has lead to certain disadvantageous developments including uneven device surfaces, which become more prominent as additional levels are added to multilevel-interconnection schemes and circuit features are scaled to submicron dimensions. Typically, each level within the device is patterned, resulting in a surface with varied step-heights where metal forming the pattern remains on the surface.
Planarization is a term describing the surface geometry of a semiconductor device. Complete planarization occurs when the surface of the dielectric is flat, as in a plane. No planarization occurs when the surface of the dielectric directly models the surface of the metal pattern in the layer underneath. The degree of planarization refers to the degree to which the varied surface geometry can be planarized, or smoothed out into a planar surface. Varied surface geometry is often undesirable. Therefore, as additional layers are formed within devices, the required degree of planarization increases.
A commonly-used planarization process in semiconductor device manufacturing is chemical-mechanical polishing, or CMP. CMP is useful in the planarization of silicon wafers and of VLSI circuits between different manufacturing processes. CMP is a popular planarization method, due in part to its usefulness in the global planarization of semiconductor devices. Traditional planarization processes are restricted to effecting local planarity or topographical variation on a small scale, whereas CMP is often useful on a global scale greater than about ten microns, depending upon the CMP tool being used.
A CMP tool commonly includes a table for securing a wafer-polishing pad with a semiconductor wafer in a wafer holder arranged opposite the wafer-polishing pad. Typically, the wafer is located face-down on the polishing pad, and both the polishing pad and the wafer holder rotate. A slurry, typically including SiO2 particles, is applied using a wand feeding to the wafer holder and pad. The rate of removal of material from the wafer is a combination of chemical and mechanical rates. The mechanical removal rate is roughly proportional to the pressure and the relative velocity of the wafer. The chemical removal rate is a function of the size of the slurry particles and the slurry solution pH.
In addition to the use of slurry in the CMP process, a conditioner is typically used for conditioning the polishing pad. The conditioner aids in the CMP polishing process and contributes to the longevity of the pad.
A problem arises in connection with CMP processing when the rotating wafer carrier is in a position, relative to the rotating pad, that is considered center-offset. For example, the center-offset condition may include center-fast or center-slow conditions. The wafer carrier is in a position that is center-fast relative to the rotating pad when the center of the wafer is polished at a higher rate than the outer regions of the wafer. The wafer carrier is in a position that is center-slow relative to the rotating pad when the center of the wafer is polished at a lower rate than the outer regions of the wafer. The disparity in polishing rate of a wafer is attributable to non-uniform conditions. For example, the polish rate increases with increased pressure, increased slurry, or increased heat. When the wafer carrier is in a position relative to the rotating pad that results in higher pressure, higher heat, or increased slurry at the center of the wafer, the polish rate near the center increases relative to the polish rate near the edge.
In the past, these center-fast and center-slow conditions have been addressed by monitoring a set of wafers after each CMP run. For example, in connection with a CMP tool adapted to polish five wafers simultaneously, a run of five wafers would be polished and then inspected to determine whether they were experiencing a center-fast or a center-slow state. Upon detecting a center-fast or a center-slow state, the oscillation amplitude was adjusted to compensate.
The consequences of center-fast or center-slow conditions can be severely disadvantageous. These conditions can result in damage to the pad and/or wafers processed using the pad; such damage includes, for example: long arc type scratches and shallow micro-scratches, die thickness variation, and the die containing residual slurry particles. Such damage can result in a wafer yield lost. Moreover, with the material and labor cost of each pad being in the hundreds of dollars, excessive occurrences of pad replacements can be a significant detriment.